1. Field of the Invention
The invention relates to a flip-chip package structure and a method for manufacturing the same, and more particularly, to a flip-chip package structure with stiffeners and a method for manufacturing the same.
2. Description of the Prior Art
Following the ever-present demand for decreasing the sizes and geometries of electronic components, the high-speed requirement and miniaturization in IC packaging technology are continually rising and become a principal objective of the IC packaging technology.
The flip-chip package structure is therefore developed. Being different from traditional wire bonding packages, chips used in the flip chip package are inverted upside down on a substrate with solder bumps to provide electrical connection between the flip chip and the substrate. Thus the scales and the sizes of the package structures are efficiently decreased while its operation for high-speed signals and heat dissipation are still improved.
For improving performance of package structures in order to satisfy demand for processing huge signals, a flip-chip package structure needs to accommodate more semiconductor chips, or to enlarge the size of the chip for containing more electric devices. However, due to the different coefficients of thermal expansion (CTE) between the chip and the substrate, the large-scaled flip-chip package structure is apt to bend during thermal treatment processes such as reflow process or curing process, and accordingly the coplanarity of the flip-chip package structure is adversely effected. In addition, such problem is not easily controlled during manufacturing process, especially in the manufacturing process of the flip-chip package structure. Therefore the problem of unfavorable coplanarity of the large-scaled flip-chip package structure is a problem that is in need of an immediate solution.
Please refer to FIG. 1, which is a schematic drawing of a conventional flip-chip package structure. The flip-chip package structure comprises a substrate 30, a chip 40 having a plurality of solder bumps 50 for electrically connecting the chip 40 to the substrate 30, and a stiffener 20 positioned on a surface of the substrate 30. The flip-chip package structure also comprises an under-fill 70 formed in between the substrate 30 and the chip 40 and encapsulating the solder bumps 50, and a lid 10 positioned on the stiffener 20 and the chip 40. The lid 10 can be a heat slug. The stiffener 20 is ring-shaped and positioned in the periphery of the chip 40.
Please refer to FIG. 2, which is a flow chart of a conventional method for manufacturing a flip-chip package structure. The method comprises:
Step S200: providing a substrate 30.
Step S210: providing a chip 40 having a plurality of solder bumps 50, and positioning the solder bumps 50 on the substrate 30. The solder bumps 50 electrically connect the chip 40 to the substrate 30.
Step S220: providing a stiffener 20 on a surface of the substrate 30.
Step S230: dispensing an under-fill 70 in between the substrate 30 and the chip 40. The under-fill 70 encapsulates the solder bumps 50.
Step S240: providing a lid 10 on the stiffener 20 and the chip 40. The stiffener is ring-shaped and positioned in the periphery of the chip 40.
It is noteworthy that in the conventional manufacturing process of the flip-chip package structure, the chip and substrate is electrically connected by the solder bumps, then the stiffener is positioned on the substrate with the underfill dispensing afterwards. Such processes improve the cleaning effect of the flux but still suffers from substrate bending after positioning the chip on the substrate. In other words, designing and positioning of the stiffener in the conventional manufacturing process of the flip-chip package structure still has an unsolved problem: it can not simultaneously improve the coplanarity of the flip-chip package structure and the cleaning effect of the flux, which is contributive to make the underfill completely contact with the solder bumps, the chip, and the substrate in order to protect the chip.